1. Field of the Invention
The present invention relates to signal pre-distortion techniques in power amplifiers. In particular, the present invention relates to signal pre-distortion techniques used in conjunction with an integrated signal analyzer.
2. Discussion of the Related Art
Adaptive digital pre-distortion (DPD) is a technique widely used in the macro-cell base stations of “third-generation” (3G) wireless communication systems. In a 3G macro-cell base station, a power amplifier typically has 42˜48 dBm output power. In contrast, in “fourth generation” (4G) wireless communication systems, and beyond, small-cell base stations are often expected, in which a typical power amplifier has 27˜35 dBm output power. Because the output power of amplifiers in such a small-cell base station is 10˜20 dB lower than macro-cell base stations of a 3G base station, it is desirable to reduce the power consumption of a pre-distortion circuit in a 4G small-cell base station by 10˜20 dB, so as to maintain overall power efficiency. In addition, it is also desirable to reduce the cost of the pre-distortion circuit by 10%, which amounts to approximately 1% of the cost in a typical budget for a macro-cell base station.
In the prior art, adaptive digital pre-distortion techniques use expensive high-speed and high-precision analog-to-digital converters (ADCs) to acquire accurate waveforms of the output signals of a power amplifier (PA). As the non-linearity of a PA enhances the PA's output bandwidth and as an intermediate-frequency down-conversion is required for eliminating I/Q imbalance, the ADC's sampling rate in such adaptive digital pre-distortion application is typically 10 or more times the original RF bandwidth, typically between 200 to 1000 mega-samples (MS) per second for RF signals with 20˜100 MHz bandwidth (e.g. 240 MS/s for a 4-carrier WCDMA signal). In addition, to detect an out-of-band emission as low as −60 dBc, the ADC needs an effective number of bits (ENOB) of approximately 11. As a result, the prior art uses dedicated, stand-alone ADC integrated circuits with ENOB greater than 10 at 200˜1000 MS/s. However, such high-precision and high-speed ADC integrated circuits are expensive and power-consuming.
In addition to the high-speed, high-precision dedicated ADC integrated circuits having high power requirements, the signal processing algorithms that are carried out in conjunction with the ADC are also very computationally complex and intensive. Consequently, fast, power-consuming digital signal processors (DSP) are required. Such DPD circuits are too costly and require too much power to be suitable for use in a small-cell base station.
Prior art analog RF pre-distortion methods can be low-power and low-cost. However, existing analog RF pre-distortion circuits are not easily adaptable for use in small-cell base station applications for two reasons. First, the adjacent channel leakage ratio (ACLR) performance is limited by analog signal processing. Second, for small-cell base station application, the task may require integrating an analog pre-distortion circuit, which is typically designed for an older CMOS process (e.g. 0.18-μm CMOS) onto a transceiver integrated circuit that is typically designed for a newer CMOS process (e.g. 65-nm CMOS).